Negativni električni kapacitet

master's thesis

• Title (english): Negative electrical capacitance
• Author: Katarina Jurišić
• Mentor: Danko Radić (mentor)
• Committee member: Danko Radić (predsjednik povjerenstva)
• Committee member: Damir Pajić (član povjerenstva)
• Committee member: Maja Planinić (član povjerenstva)
• Committee member: Ivo Batistić (član povjerenstva)
• Committee member: Emil Tafra (član povjerenstva)
• Granter: University of Zagreb; Faculty of Science; (Department of Physics); Zagreb
• Defense date and country: 2017-07-17, Croatia
• Scientific / art field, discipline and subdiscipline: NATURAL SCIENCES; Physics

Abstract

U posljednjih nekoliko godina, u nanoelektronici se pojavio problem kontrole topline generirane procesiranjem informacija što je rezultiralo stagnacijom operativne frekvencija procesora. Izvor tog problema leži u tranzistorima, ključnoj poluvodičkoj komponenti modernih elektroničkih uređaja. Iako su se veličine tranzistora od njegovog izuma 1947. godine smanjile na nanometarsku skalu, današnje tržište zahtjeva njihovo daljnje smanjenje. No, ono će u jednom trenutku dosegnuti granicu određenu nemogućnošću uklanjanja topline generirane procesom paljenja. Smanjenje radnog napona tranzistora bi omogućilo otklanjanje tog problema čime bi se ubrzao i rad elektroničkih uređaja. Negativni električni kapacitet je proizašao kao rješenje koje omogućava smanjenje radnog napona ispod standardne vrijednosti (∼ 1 V). Kombinacija feroelektričnog materijala s linearnim dielektikom ispod upravljačke elektrode FET-a se efektivno ponaša kao serijski spoj dvaju kondenzatora, od kojih jedan ima negativni kapacitet. Cilj ovog rada je pokazati zašto kod feroelektrika dolazi do pojave negativnog električnog kapaciteta, postoji li mogućnost pristupa tom području i pod kojim uvjetima te konačno koje posljedice za tranzistore proizlaze iz toga.

Abstract (english)

In the last several years, the most difficult problem in nanoelectronics is the management of the heat generated during information processing which resulted in the processor operational frequency stagnation. The source of that problem lies in the fundamental physics of the transistors, key semiconductor component in modern electronic devices. Although transistor sizes reduced to the nanometer scale since their invention in 1947, today market requires their further reduction. But the ongoing scaling will be eventually limited by the inability to remove the heat generated in the switching process. Reducing transistor’s operational voltage would provide elimination of the mentioned problem which would also speed up electronic devices. Negative electrical capacitance has emerged as a solution which provides reduction of operational voltage below standard value (∼ 1 V). Combination of ferroelectric material and linear dielectric at the gate region of FET would effectively behave like series combination of two capacitors, of which one has negative capacitance. The main goal of this thesis is to show why does negative capacitance emerges in ferroelectrics, is there a possibility to access this region and under what conditions, and finally what are the consequences of negative capacitance on the transistors.

• Keywords: negativni električni kapacitet; feroelektrici; Landauov razvoj za feroelektrike; Landau-Khalatnikova jednadžba; tranzistori
• Keywords (english): negative electrical capacitance; ferroelectrics; Landau primer for ferroelectrics; Landau-Khalatnikov equation; tranzistors
• Language: croatian
• URN:NBN: urn:nbn:hr:217:698906
• Study programme: Title: Physics; specializations in: Education; Course: Education; Study programme type: university; Study level: integrated undergraduate and graduate; Academic / professional title: magistar/magistra edukacije fizike (magistar/magistra edukacije fizike)
• Type of resource: Text
• File origin: Born digital
• Access conditions: Open access
• Created on: 2017-08-01 09:12:41